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a ad9057 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. rev. d 8-bit 40 msps/60 msps/80 msps a/d converter functional block diagram adc t/h 8 d7?0 encode ain vref out bias out v d pwrdn v dd ad9057 vref in 2.5v 1k gnd product description the ad9057 is an 8-bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. with 40 msps, 60 msps, or 80 msps encode rate capability and full-power analog bandwidth of 120 mhz, the component is ideal for applications requiring excellent dynamic performance. to minimize system cost and power dissipation, the ad9057 includes an internal 2.5 v reference and a track-and-hold (t/h) circuit. the user must provide only a 5 v power supply and an encode clock. no external reference or driver components are required for many applications. the ad9057? encode input is ttl/cmos compatible, and the 8-bit digital ou tputs can be operated from 5 v or 3 v sup plies. a power-down function may be exercised to bring total consump tion to <10 mw. in power-down mode, the digital outputs are driven to a high impedance state. fabricated on an advanced bicmos process, the ad9057 is available in a space-saving 20-lead shrink small outline package (20-lead ssop) and is specified over the i ndustrial temperature range (?0 c to +85 c). customers desiring multichannel digitization may consider the a d9059, a dual 8-bit, 60 msps monolithic based on the ad 9057 adc core. the ad9059 is available in a 28-lead sur- face-mount plastic package (28-lead ssop) and is specified over the industrial temperature range. features 8-bit, low power adc: 200 mw typical 120 mhz analog bandwidth on-chip 2.5 v reference and track-and-hold 1 v p-p analog input range single 5 v supply operation 5 v or 3 v logic interface power-down mode: <10 mw 3 performance grades (40 msps, 60 msps, 80 msps) applications digital communications (qam demodulators) rgb and yc/composite video processing digital data storage read channels medical imaging digital instrumentation
rev. d ? ad9057?pecifications (v d = 5 v, v dd = 3 v; external reference, unless otherwise noted.) test AD9057BRS-40 ad9057brs-60 ad9057brs-80 parameter temp level min typ max min typ max min typ max unit resolution 8 8 8 bits dc accuracy differential nonlinearity 25 ci 0.75 1.9 0.75 1.9 0.75 1.9 lsb full vi 2.0 2.0 2.0 lsb integral nonlinearity 25 ci 0.75 1.9 0.75 1.9 0.75 1.9 lsb full vi 2.0 2.0 2.0 lsb no missing codes full vi guaranteed guaranteed guaranteed gain error 1 25 ci ? ?.5 +6 ? ?.5 +6 ? ?.5 +6 % fs full vi ? +8 ? +8 ? +8 % fs gain tempco 1 full v 70 70 70 ppm/ c analog input input voltage range (centered at 2.5 v) 25 cv 1.0 1.0 1.0 v p-p input offset voltage 25 ci ?5 0 +15 ?5 0 +15 ?5 0 +15 mv full vi ?5 +25 ?5 +25 ?5 +25 mv input resistance 25 cv 150 150 150 k w input capacitance 25 cv 222pf input bias current 25 ci 6 16 6 16 6 16 m a full vi 25 25 25 m a analog bandwidth 25 cv 120 120 120 mhz band gap reference output voltage full vi 2.4 2.5 2.6 2.4 2.5 2.6 2.4 2.5 2.6 v temperature coefficient full v 10 10 10 ppm/ c switching performance maximum conversion rate full vi 40 60 80 msps minimum conversion rate full iv 5 5 5 msps aperture delay (t a )25 cv 2.7 2.7 2.7 ns aperture uncertainty (jitter) 25 cv 555ps rms output valid time (t v ) 2 full iv 4.0 6.6 4.0 6.6 4.0 6.6 ns output propagation delay (t pd ) 2 full iv 11.5 18.0 9.5 14.2 8.0 11.3 ns dynamic performance 3 transient response 25 cv 999ns overvoltage recovery time 25 cv 999ns signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz 25 ci 42 45.5 42 45 41.5 45 db f in = 76 mhz 25 cv 44.0 43.5 43.5 db effective number of bits (enob) f in = 10.3 mhz 25 ci 6.7 7.2 6.7 7.2 6.6 7.2 bits f in = 76 mhz 25 cv 7.0 6.9 6.9 bits signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25 ci 43 46.5 43 46 42.5 46 db f in = 76 mhz 25 cv 45.5 45 45 db second harmonic distortion f in = 10.3 mhz 25 ci ?0 ?2 ?0 ?2 ?0 ?2 dbc f in = 76 mhz 25 cv ?4 ?4 ?4 dbc third harmonic distortion f in = 10.3 mhz 25 ci ?6 ?0 ?6 ?0 ?6 ?0 dbc f in = 76 mhz 25 cv ?4 ?4 ?4 dbc two tone intermodulation distortion (imd) 25 cv ?2 ?2 ?2 dbc differential phase 25 cv 0.8 0.8 0.8 degrees differential gain 25 cv 1.0 1.0 1.0 % digital inputs logic 1 voltage full vi 2.0 2.0 2.0 v logic 0 voltage full vi 0.8 0.8 0.8 v logic 1 current full vi 1 1 1 m a logic 0 current full vi 1 1 1 m a input capacitance 25 cv 4.5 4.5 4.5 pf encode pulsewidth high (t eh )25 civ 9.0 166 6.7 166 5.5 166 ns encode pulsewidth low (t el )25 civ 9.0 166 6.7 166 5.5 166 ns
rev. d ? ad9057 test AD9057BRS-40 ad9057brs-60 ad9057brs-80 parameter temp level min typ max min typ max min typ max unit digital outputs logic 1 voltage (v dd = 3 v) full vi 2.95 2.95 2.95 v logic 1 voltage (v dd = 5 v) full iv 4.95 4.95 4.95 v logic 0 voltage full vi 0.05 0.05 0.05 v output coding offset binary code offset binary code offset binary code power supply v d supply current (v d = 5 v) full vi 36 48 38 48 40 51 ma v dd supply current (v dd = 3 v) 4 full vi 4.0 6.5 5.5 6.5 7.4 8.8 ma power dissipation 5, 6 full vi 192 260 205 260 220 281 mw power-down dissipation full vi 6 10 6 10 6 10 mw power supply rejection ratio (psrr) 25 cv 333 mv/v notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 2.5 v external reference). 2 t v and t pd are measured from the 1.5 v level of the encode to the 10%/90% levels of the digital output swing. the digital output load dur ing test is not to exceed an ac load of 10 pf or a dc current of 40 m a. 3 snr/harmonics based on an analog input voltage of ?.5 dbfs referenced to a 1.0 v full-scale input range. 4 digital supply current based on v dd = 3 v output drive with <10 pf loading under dynamic test conditions. 5 power dissipation is based on specified encode and 10.3 mhz analog input dynamic test conditions (v d = 5 v 5%, v dd = 3 v 5%). 6 typical thermal impedance for the rs style (ssop) 20-lead package : q jc = 46 c/w, q ca = 80 c/w, and q ja = 126 c/w. specifications subject to change without notice. n n + 3 n + 1 n + 2 n + 4 n + 5 ain encode digital outputs t a t eh t el t v t pd n ?3 n ?2 n ?1 n n + 1 n + 2 aperture delay pulsewidth high pulsewidth low output valid time output prop delay t a t eh t el t v t pd 4.0 ns 2.7 ns 6.6 ns 9.5 ns 166 ns 166 ns min typ max figure 1. timing diagram explanation of test levels test level description i 100% production tested. ii 100% production tested at 25 c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and charac- terization testing. vp arameter is a typical value only. vi 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range.
rev. d ad9057 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9057 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v analog inputs . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . ?.5 v to v dd + 0.5 v vref input . . . . . . . . . . . . . . . . . . . . . . ?.5 v to v d + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c maximum case temperature . . . . . . . . . . . . . . . . . . . 150 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature model range package op tion * AD9057BRS-40 40 c to +85 c rs-20 ad9057brs-60 40 c to +85 c rs-20 ad9057brs-80 40 c to +85 c rs-20 ad9057/pcb 25 ce valuation board * rs = shrink small outline package (ssop). table i. digital coding (vref = 2.5 v) analog input voltage level digital output 3.0 v positive full scale 1111 1111 2.502 v midscale +1/2 lsb 1000 0000 2.498 v midscale ?/2 lsb 0111 1111 2.0 v negative full scale 0000 0000 pin function descriptions pin no. mnemonic function 1 pwrdn power-down function select; logic high for power-down mode (digital outputs go to high impedance state). 2 vref out internal reference output (2. 5 v typ); bypass with 0.1 m f to ground. 3 vref in refer ence input for adc (2.5 v t yp, 10%). 4, 9, 16 gnd ground (analog/digital). 5, 8 v d analog 5 v power supply. 6 bias out bias pin for ac coupling (1 k w to ref in). 7 ain analog input for adc. 10 encode encode clock for adc (adc samples on rising edge of encode). 1 1?4, 1720 d7?0 digital outputs of adc. 15 v dd digital output power supply; nominally 3 v to 5 v. pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) pwrdn d3 d2 d1 d0 (lsb) vref out vref in gnd ad9057 d4 v dd gnd v d bias out ain v d gnd encode d7 (msb) d6 d5
rev. d ? t ypical performance characteristicsad9057 0 ?0 ?0 030 db ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 60msps analog in = 10.3mhz, ?.5dbfs sinad = 46.1db enob = 7.36 bits snr = 46.5db frequency ( mhz ) tpc 1. spectral plot 60 msps, 10.3 mhz 0 ?0 ?0 030 db ?0 ?0 ?0 ?0 ?0 ?0 ?0 frequency (mhz) encode = 60msps analog in = 76mhz, ?.5dbfs sinad = 44.9db enob = 7.16 bits snr = 45.2db tpc 2. spectral plot 60 msps, 76 mhz analog input frequency ( mhz ) db 0 160 20 40 60 80 100 120 140 48 46 30 38 36 34 32 42 40 44 encode = 60msps ain = ?.5dbfs snr sinad tpc 3. sinad/snr vs. ain frequency analog input frequency (mhz) db ?0 ?0 0 160 20 40 60 80 100 120 140 ?5 ?0 ?5 ?0 ?5 ?0 ?5 encode = 60msps ain = ?.5dbfs third harmonic second harmonic tpc 4. harmonic distortion vs. ain frequency frequency (mhz) db 0 ?0 ?0 030 10 20 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 60msps f1 in = 9.5mhz @ ?.0dbfs f2 in = 9.9mhz @ ?.0dbfs 2f1 ?f2 = ?2.0dbc 2f2 ?f1 = ?3.0dbc tpc 5. two-tone intermodulation distortion encode rate (msps) 54 24 0 510203 04050607080 90 48 30 18 42 36 ain = 10.3mhz, ?.5dbfs snr sinad db 12 tpc 6. sinad/snr vs. encode rate
rev. d ad9057 ? encode rate (msps) mw 350 150 0 5102030405 060708090 300 250 100 50 200 v dd = 5v v dd = 3v ain = 10.3mhz, ?.5dbfs tpc 7. power dissipation vs. encode rate temperature ( c) 46.5 db 46.0 41.5 ?5 90 02570 44.5 43.0 42.5 42.0 45.5 45.0 43.5 44.0 snr sinad encode = 60msps ain = 10.3mhz, ?.5dbfs tpc 8. sinad/snr vs. temperature temperature ( c) 0 gain error (%) ?.2 ?.8 ?5 90 02570 ?.8 ?.2 ?.4 ?.6 ?.4 ?.6 ?.0 tpc 9. adc gain vs. temperature (with external 2.5 v reference) temperature ( c) 10.0 t pd (ns) 9.5 ?5 90 02570 8.0 6.5 6.0 9.0 8.5 7.0 7.5 v dd = 5v v dd = 3v 11.0 12.0 tpc 10. t pd vs. temperature/supply (v dd = 3 v/5 v) encode high pulsewidth ( ns ) db 46.5 42.5 5.8 9.2 8.35 45.0 44.0 43.5 43.0 46.0 45.5 44.5 sinad snr encode = 60msps ain = 10.3mhz, ?5dbfs 10.0 10.9 6.7 7.5 43.5 tpc 11. sinad/snr vs. encode pulsewidth adc gain (db) 0 ? ?0 110 100 ? ? ? ? 25 20 50 200 500 encode = 60msps ain = ?.5dbfs ? ? ? ? analog frequency (mhz) tpc 12. adc frequency response
rev. d ad9057 ? theory of operation the ad9057 combines analog devices?proprietary magamp gray code conversion circuitry with flash converter technology to provide a high performance, low cost adc. the design ar chitecture ensures low power, high speed, and 8-bit accuracy. a single-ended ttl/cmos compatible encode input controls adc timing for sampling the analog input pin and strobing the digital outputs (d7?0). an internal voltage reference (vref out) may be used to control adc gain and offset or an exter- nal reference may be applied. the analog input signal is buffered at the input of the adc and applied to a high speed track-and-hold. the track-and-hold circuit holds the analog input value during the conversion pro cess (beginning with the rising edge of the encode command). the track-and-hold? output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. decode logic combines the multistage data and aligns the 8-bit word for strobed outputs on the rising edge of the encode command. the magamp/flash architecture of the ad9057 results in three pipeline delays for the output data. using the ad9057 analog inputs the ad9057 provides a single-ended analog input impedance of 150 k w . the input requires a dc bias current of 6 m a (typical) centered near 2.5 v ( 10%). the dc bias may be provided by the user or may be derived from the adc? internal voltage reference. figure 2 shows a low cost dc bias implementation allowing the user to capacitively couple ac signals directly into the adc without additional active circuitry. for best dynamic performance, the vref out pin should be decoupled to ground with a 0.1 m f capacitor (to minimize modulation of the refer ence voltage) and the bias resistor should be approxi- mately 1 k w . a 1 k w bias resistor ( 20%) is included within the ad 9057 and may be used to reduce application board size and complexity. ad9057 vref out ain 0.1 f 5v vin (1v p-p) vref in bias out 1k 0.1 f figure 2. capacitively coupled ad9057 figure 3 shows typical connections for high performance dc biasing using the adc? internal voltage reference. all compo- nents may be powered from a single 5 v supply. in the example, analog input signals are referenced to ground. ad9057 vref out vref in ain 0.1 f 10k 10k ad8041 5v 1k 5v 1k vin (?.5v to +0.5v) figure 3. dc-coupled ad9057 (inverted vin) voltage reference a stable and accurate 2.5 v voltage reference is built into the ad9057 (vref out). the reference output may be used to s et the adc gain/offset by connecting vref out to vref in. the internal reference is capable of providing 300 m a of drive current (for dc biasing the analog input or other user circuitry). some applications may require greater accuracy, improved temperature performance, or gain adjustments that cannot be obtained using the internal reference. an external voltage may be applied to the vref in with vref out disconnected for gain adjustment of up to 10% (the vref in pin is internally ti ed directly to the adc circuitry). adc gain and offset will vary simultaneously with external reference adjustment with a 1 :1 ratio (a 2% or 50 mv adjustment to the 2.5 v reference varies adc gain by 2% and adc input range center offset by 50 mv). t heoretical input voltage range versus reference input voltage may be calculated from the following equations: v range (p-p) = vref in/ 2.5 v midscale = vref in v top-of-range = vref in + v range /2 v bottom-of-range = vref in ?v range /2 digital logic (5 v/3 v systems) the digital inputs and outputs of the ad9057 can easily be configured to interface directly with 3 v or 5 v logic systems. the encode and power-down (pwrdn) inputs are cmos stages with ttl thresholds of 1.5 v, making the inputs compat- ible with ttl, 5 v cmos, and 3 v cmos logic families. as with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of adc dynamic performance. the ad9057? digital outputs will also interface directly with 5v or 3 v cmos logic systems. the voltage supply pin (v dd ) for these cmos stages is isolated from the analog v d voltage s upply. by varying the voltage on this supply pin, the digital output high level will change for 5 v or 3 v systems. optimum s nr is obtained running the outputs at 3 v. care should be taken to isolate the v dd supply voltage from the 5 v analog supply to minimize digital noise coupling into the adc.
rev. d ad9057 ? the ad9057 provides high impedance digital output operation when the adc is driven into power-down mode (pwrdn, logic high). a 200 ns (minimum) power-down time should be provided before a high impedance characteristic is required at the outputs. a 200 ns power-up period should be provided to ensure accurate adc output data after reactivation (valid out- put data is available three clock cycles after the 200 ns delay). timing t he ad9057 is guaranteed to operate with conversion rates from 5 msps to 80 msps depending on grade. the adc is de signed to operate with an encode duty cycle of 50%, but performance is insensitive to moderate variations. pulsewidth variations of up to 10% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degradation in adc performance (see figure 1 timing diagram). power dissipation the power dissipation of the ad9057 is specified to reflect a typical application setup under the following conditions: analog i nput is ?.5 dbfs at 10.3 mhz, v d is 5 v, v dd is 3 v, and digital outputs are loaded with 7 pf typical (10 pf maximum). the actual dissipation will vary as these conditions are modified in user applications. tpc 7 shows typical power consumption for the ad9057 versus adc encode frequency and v dd supply voltage. a power-down function allows users to reduce power dissipation when adc data is not required. a ttl/cmos high signal (pwrdn) shuts down portions of the adc and brings total power dissipation to less than 10 mw. the internal band gap voltage reference remains active during power-down mode to minimize adc reactivation time. if the power-down function is not desired, pin 1 should be tied to ground. applications the wide analog bandwidth of the ad9057 makes it attractive for a variety of high performance receiver and encoder applications. f igure 4 shows two adcs in a typical low cost i and q dem odula- tor implementation for cable, satellite, or wireless lan modem re ceivers. the excellent dynamic performance of the adc at higher analog input frequencies and encode rates empowers users to employ direct if sampling techniques (refer to tpc 2 spectral plot). if sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. bpf bpf ad9057 ad9057 vco 90 vco if in figure 4. i and q digital receiver the high sampling rate and analog bandwidth of the ad9057 are ideal for computer rgb video digitizer applications. with a full-power analog bandwidth of 2 the maximum sampling rate, the adc provides sufficient pixel-to-pixel transient settling time to ensure accurate 60 msps video digitization. figure 5 shows a typical rgb video digitizer implementation for the ad9057. ad9057 ad9057 pll ad9057 pixel clock red green blue h-sync 8 8 8 figure 5. rgb video encoder evaluation board the ad9057/pcb evaluation board provides an easy-to-use analog/digital interface for the 8-bit, 60 msps adc. the board includes typical hardware configurations for a variety of high speed digitization evaluations. on-board components include the ad9057 (in the 20-lead ssop package), an optional analog input buffer amplifier, a digital output latch, board timing drivers, an analog reconstruction digital-to-analog converter, and config- urable jumpers for ac coupling, dc coupling, and power-down function tes ting. the board is configured at shipment for dc coupling using the ad9057? internal voltage reference. for dc-coupled analog input applications, amplifier u2 is con- figured to operate as a unity gain inverter with adjustable offset for the analog input signal. for full-scale adc drive, the analog input signal should be 1 v p-p into 50 w (r1) referenced to ground (0 v). the amplifier offsets the analog signal by +vref (2.5 v typical) to center the voltage for proper adc input drive. for dc-coupled operation, connect e1 to e2 (analog input to r2) and e11 to e12 (amplifier output to analog input of ad 9057) using the board jumper connectors. dc offset of the analog input signal can be modified by adjusting potentiometer r10. for ac-coupled analog input applications, amplifier u2 is removed from the analog signal path. the analog signal is coupled into the input of the ad9057 through capacitor c2. the adc pulls analog input bias current from the vref in voltage through the 1 k w resistor internal to the ad9057 (bias out). the analog input signal to the board should be 1 v p-p into 50 w (r1) for full-scale adc drive. for ac-coupled op eration, connect e1 to e3 (analog input a to c2 feedthrough capacitor) and e10 to e12 (c2 to the analog input and internal bias resis- tor) using the board jumper connectors. the on-board reference voltage may be used to drive the adc or an external reference may be applied. to use the internal voltage reference, connect e6 to e5 (vref out to vref in). to apply an external voltage reference, connect e4 to e5 (external reference from the ref banana jack to vref in). the external voltage reference should be 2.5 v 10%.
rev. d ad9057 ? the power-down function of the ad9057 can be done through a board jumper connection. connect e7 to e9 (5 v to pwrdn) for power-down operation. for normal operation, connect e8 to e9 (ground to pwrdn). the encode signal source should be ttl/cmos compatible and capable of driving a 50 w termination (r7). the digital outputs of the ad9057 are buffered through latches on the evaluation board (u3) and are available for the user at connector pins 30 to 37. latch timing is derived from the adc encode clock and a digital clocking signal is provided for the board user at connector pins 2 and 21. an on-board reconstruction digital-to-analog converter is available for quick evaluations of adc performance using an oscilloscope or spectrum analyzer. the dac converts the adc? digital outputs to an analog signal for examination at the dac out connector. the dac is clocked at the adc encode fre quency. the ad9760 is a 10-bit/100 msps single 5 v supply dac. the reconstruction signal facilitates quick system trouble- shooting or confirmation of adc functionality without requiring external digital memory, timing, or display interfaces. the dac can be used for limited dynamic testing, but customers should note t hat test results will be based on the combined performance of the adc and dac (the best adc performance will be recognized by evaluating the digital outputs of the adc directly). v d encode pwrdn d0?7 v dd , 3v to 5v v d v ref out v ref in 1k v d bias out v d 3k v ref in 2.5k 500 v d v ref in ain digital inputs analog input digital outputs bias output v ref output v ref input figure 6. equivalent circuits
rev. d ad9057 ?0 u4 74ac00 1 2 3 u4 74ac00 4 5 6 u4 74ac00 12 13 11 u4 74ac00 9 10 8 r7 50 pwrdn vref out vref in gnd v d bias out ain v d gnd enc 1 2 3 4 5 6 7 8 9 10 ( lsb) d0 d1 d2 d3 gnd v dd d4 d5 d6 ( msb) d7 20 19 18 17 16 15 14 13 12 11 d0 d1 d2 d3 gnd v dd d4 d5 d6 d7 gnd 5v 5v gnd e12 e11 e10 c2 0.1 f r6 10 c1 0.1 f e4 e5 e6 j6, ref gnd pwrdn 5v e7 e9 e8 r5 2k r10 500 r4 2k 8 7 6 5 dis +v s nc nc ? s u2 ad8041q c17 0.1 f 1 r2 1k e2 r1 50 bnc j1 analog in db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 2 3 4 5 6 7 8 9 10 ( lsb) ( msb) clock dvdd avdd comp2 comp1 fs adj refio reflo sleep iout ab 28 dac ad9760ar 27 24 23 19 18 17 16 15 da7 da6 da5 da4 da3 da2 da1 da0 gnd gnd 22 21 pwrdn 5v 5v 5v c18 0.1 f c19 0.1 f r9 2k c13 0.1 f r11 50 r8 50 bnc j2 1 2 3 4 5 6 7 8 c37drpf p2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 da0 da1 da2 da3 da4 da5 da6 da7 8d 7d 6d 5d 4d 3d 2d 1d 12 13 14 15 16 17 18 19 8q 7q 6q 5q 4q 3q 2q 1q 9 8 7 6 5 4 3 2 ck oe 1 11 d7 d6 d5 d4 d3 d2 d1 d0 da7 da6 da5 da4 da3 da2 da1 da0 u3 74acq574 r3 1k bnc j3 encode analog reconstruct dac out c11 10 f c10 0.1 f + j7, v dd v dd j4, gnd c14 0.1 f c8 0.1 f c7 0.1 f c12 10 f c9 0.1 f c5 0.1 f c4 0.1 f + c3 0.1 f j5, 5v decoupling caps 2 3 4 e1 e3 ad9057 figure 7. evaluation board schematic
rev. d ad9057 ?1 figure 8. evaluation board layout
rev. d ?2 c00561??/03(d) ad9057 20-lead shrink small outline package [ssop] (rs-20) dimensions shown in millimeters 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 coplanarity 0.10 0.05 min 1.85 1.75 1.65 0.65 bsc 0.25 0.09 0.95 0.75 0.55 8 4 0 2.00 max 0.38 0.22 seating plane compliant to jedec standards mo-150ae outline dimensions revision history location page 5/03?ata sheet changed from rev. c to rev. d. change to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9/01?ata sheet changed from rev. b to rev. c. edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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